In recent years, as the degree of integration has increased, the design rule for the whole process of making the gate electrode, the source/drain region, and the contact holes of a MOSFET has decreased. However, the operating speed of the semiconductor device decreases as the width of its gate electrode, (which is inversely proportional to electric resistance), increases. Polycrystalline silicon/oxide shows the most stable MOSFET characteristics. Therefore, to reduce the electric resistance of the gate electrode, a polycide structure (i.e., a composite structure comprising a silicide layer and a polycrystalline silicon layer) has been used as a low resistance gate with the desired interface characteristics.
A pn junction is formed by implanting n-type or p-type impurities into a p-type or n-type semiconductor substrate. More specifically, the pn junction is fabricated by implanting impurity ions into a semiconductor substrate, and thermally activating the implantation region to form diffusion region(s). A semiconductor device with a narrow width channel should be formed with a shallow depth junction to prevent a short channel effect due to side diffusion from the diffusion region. The source/drain regions of the semiconductor device are also formed as a Lightly Doped Drain (hereinafter referred to as “LDD”) structure in order to prevent junction breakdown by a field enhancement effect into the drain and a change of a threshold voltage by a thermal charge effect.
A prior art method of fabricating a MOSFET comprises forming a gate oxide layer over a p-type silicon wafer of a semiconductor substrate, forming a gate electrode of a polycrystalline silicon layer piled by a mask oxide layer (i.e., by an insulating pattern over the gate oxide layer), forming LDD regions over the semiconductor substrate adjacent the sides of the gate electrode, forming spacers on the sidewalls of the gate electrode, and then forming source/drain regions by implanting high density impurities into the surface of the substrate adjacent the sides of the spacers.
However, the above-mentioned prior art method suffers from shortcomings such as a high possibility of a gate oxide integrity (hereinafter referred to as “GOI”) failure due to the formation of a thin or abnormal gate insulating layer around the supporting edges of the gate electrode, and deteriorated reliability of the semiconductor device due to dopant penetration of the insulating layer during the formation process of an insulating layer or the later thermal process.
Rodder et al., U.S. Pat. No. 6,251,761, describes a method of fabricating an integrated circuit MOSFET transistor. A method described in the '761 Patent comprises forming a high-k dielectric over a silicon substrate, performing remote plasma nitridation of the high-k dielectric to create a nitride layer over the high-k dielectric, and then forming a conductive layer over the nitride layer forming the gate electrode.